Architecture, design, and modeling of the OPSnet asynchronous optical packet switching node

An all-optical packet-switched network supporting multiple services represents a long-term goal for network operators and service providers alike. The EPSRC-funded OPSnet project partnership addresses this issue from device through to network architecture perspectives with the key objective of the design, development, and demonstration of a fully operational asynchronous optical packet switch (OPS) suitable for 100 Gb/s dense-wavelength-division multiplexing (DWDM) operation. The OPS is built around a novel buffer and control architecture that has been shown to be highly flexible and to offer the promise of fair and consistent packet delivery at high load conditions with full support for quality of service (QoS) based on differentiated services over generalized multiprotocol label switching

A multi-exit recirculating optical packet buffer

We propose a new type of recirculating buffer, the multiexit buffer (MEB), for use in asynchronous optical packet switches with statistical multiplexing, operating at speeds of 40-100 Gb/s. We demonstrate that the use of this type of buffer dramatically reduces the packet loss for a given buffer depth, thus reducing the buffer depth requirements and the overall cost of the optical packet switching. Physical layer simulation results show that it is possible to build this type of buffer with currently available active components. A hybrid optoelectronic control system is proposed, which allows control of the MEB with a minimum number of active components

An analytical performance model for the Spidergon NoC

Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect networks to handle the increasing communication requirements of the large systems on chip. Employing an appropriate topology for a NoC is of high importance mainly because it typically trade-offs between cross-cutting concerns such as performance and cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [7]. In this paper we analyze the traffic behavior in the spidergon scheme and present an analytical evaluation of the average message latency in the architecture. We prove the validity of the analysis by comparing the model against the results produced by a discreteevent simulator

Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring

The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. Debugging and performance evaluation of such complex designs can be significantly improved through debug information that provides a system-level perspective and hides the complexity of signal-level debugging. In this paper we present a debugging system that permits transaction-based communication-centric monitoring of packet processing systems. We demonstrate, using two different examples, how this system can improve the debugging information and abstract lower level detail. Furthermore, we demonstrate that transaction monitoring systems require fewer resources than conventional RTL debugging systems and can provide a system-level perspective not permitted by traditional tools

A type system for static typing of a domain-specific language

With the increase in system complexity, designers are increasingly using IP blocks as a means for filling the designer productivity gap. This has given rise to system level languages which connect IP blocks together. However, these languages have in general not been subject to formalisation. They are considered too trivial to justify the formalisation effort. Unfortunately, the lack of formality in these languages can give rise to errors that are not caught until late in the design cycle. We present a type system for static typing of such a system level language. We argue that the proposed type system will eliminate an important class of errors currently permitted by existing system level languages. A comparison is made against existing tools and we show that the type checker detects errors earlier in the design flow. This reduces synthesis iterations and decreases the time to market

Automated instrumentation of FPGA-based systems for system-level transaction monitoring

Modern FPGA-based systems are complex and difficult to verify. One approach to easing the verification problem and reducing perceived complexity is to use libraries of reusable functions. These reusable functions, known as intellectual property blocks, are commonly created as netlists or RTL components. Complex systems can be created from IP blocks by using high-level design environments. These tools define the types and semantics of component interfaces which permit systems to be debugged using system-level transaction monitoring. However, the insertion of on-chip monitoring circuitry is a manual process in FPGA design flows. In this paper we present an algorithm which exploits the high-level design environment to permit automatic instrumentation of designs. We demonstrate that the algorithm can harness existing HDL generation techniques and reduce the insertion and configuration effort required of the designer

Architectural comparison of instruments for transaction level monitoring of FPGA-based packet processing systems

The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. To facilitate debugging and performance evaluation, designers require on-chip monitors that provide abstractions of low-level details and a system-level perspective. In this paper, we present five architectures that permit transaction-based communication-centric monitoring of packet processing systems. We compare the resource requirements and filtering functionality of each architecture, demonstrating that sequential matching is more resource efficient than parallel matching. We also show that generic filtering has a low overhead compared to specialised filtering while providing additional flexibility. A scalable architecture is also presented, which is more flexible and adaptable to matching requirements than other architectures. These monitoring architectures permit the implementation of a highly effective test system which provides a system-level perspective and is more resource efficient than conventional RTL debug environments

Optimization of On-Chip Link Performance under Area, Power and Variability Constraints

A large number of repeaters are used in the global interconnects of any System-on-Chip (SoC) design for improving the delay characteristics, and these repeaters consume a significant portion of the chip area and power. In this work we emphasize that due to increasing trend of the variability, power and area optimal repeater insertion methodologies should also consider performance variability. Analytical models for area, power, performance and probability of link failure have been presented in terms of the size of the repeaters and inter-repeater segment length. It has been found that beyond a certain reduction in the size of the repeaters, the delay variability may exceed acceptable limits while still satisfying other constraints. For instance, with only 4% of performance loss due to the use of smaller repeaters, almost 30% of power and 40% of area savings can be achieved; however performance certainty is reduced by 24%. Therefore, while optimizing area, power and performance of on-chip communication links, delay (and power) variability should also be included in the figure of merit